ROM logic design?

Question

You are asked to design a comparator circuit that has an input of two 2-bit 

numbers. The comparator has 3 outputs, representing the cases where the first number 

(A1A2) is equal to the second number (B1B0) (in this case E should equal 1), smaller than 

the second number (in this case L equals 1), and greater than the second number (G 

equals 1), respectively. Complete the Truth Table below to define E, L and G. If the 

comparator is realized with a ROM, what size of ROM is required? (i.e.: how many bits?) 

Assuming the ROM below is used to generate all minterms, use dots to indicate 

connections which realize each of the required functions.

Answer 1

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The ROM will have a total of four input (address) signals, the 2+2 bit numbers.

That's 2^4 combinations; 16.

Three output signals, so three bits used at each address = 48 bits used in total.

To work it out, make a 4x4 grid with one number across the top 0-3 and the other 0-3 down the side.

Write the e-l-g output bit state for each combination in the grid.

Then, if you use the top number for the lower two address bits and the side number for the higher two, just take the grid content working left to right and top to bottom.

That gives you 16 results for all the input combinations, in sequence.

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Answer 2

I DID THE truth table it  involves  4 inputs  and  3 outputs  only  one output active at any time..

16 inputs   these can be address inputs 

the outputs can be the data  so you need  3  data bits  fore each address 

so  48 bit rom is  fine  

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